1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of selective epitaxial growth for a semiconductor device.
2. Description of the Related Art
As integrated circuit devices become more highly integrated and include finer geometries, the width and spacing between interconnections have also been reduced. In order to avoid misalignment problems associated with highly integrated circuit devices, a self-alignment technology has been required.
A selective epitaxial growth technique has been suggested as one of the self-alignment techniques. The selective epitaxial growth technique is mainly used to grow a semiconductor layer such as a silicon layer or a germanium layer on a predetermined region of a semiconductor substrate.
Japanese Laid-open Patent No. 4139819 discloses a method of selectively growing a silicon layer by alternately and repeatedly injecting disilane (Si2H6) gas and chlorine (Cl2) gas into a chamber in which a silicon substrate is loaded. Here, the disilane gas is used as a silicon source gas, and the chlorine gas is used as an etching gas for removing silicon nuclei on an insulating layer.
According to the Japanese Laid-open Patent No. 4139819, chlorine atoms are adsorbed on a surface of the silicon layer grown on the silicon substrate during injection of the chlorine gas. Accordingly, the silicon layer is passivated with chlorine atoms. As a result, the silicon layer is grown very slowly, even though the silicon source gas is injected in a subsequent step.
It is therefore a feature of an embodiment of the present invention to provide a selective epitaxial growth method, which is capable of improving a growth selectivity as well as a growth rate.
It is another feature of an embodiment of the present invention to provide a selective epitaxial growth method, which is capable of removing defects due to the etching gas.
It is still another feature of an embodiment of the present invention to provide a selective epitaxial growth method, which is capable of easily adjusting a doping concentration of impurities by using an in-situ doping method.
These features can be provided by a selective epitaxial growth method in fabrication of a semiconductor device. This method comprises loading a semiconductor substrate having an insulating layer pattern on a predetermined region of the semiconductor substrate into a chamber and repeatedly (at least two times) performing the growth process, wherein each of the growth processes includes three steps of sequentially injecting a source gas, an etching gas and a reducing gas. The insulating layer pattern may correspond to an isolation layer formed at a predetermined region of the semiconductor substrate. Also, the insulating layer may further include a capping layer covering a top surface and a spacer covering a sidewall of a gate electrode.
After loading the semiconductor substrate into the chamber, the chamber is evacuated using a vacuum pump, to maintain a pressure lower than atmospheric pressure, and then the semiconductor substrate is heated and maintained at a predetermined temperature. The source gas is then injected into the chamber. Here, the source gas comprises a gas for growing a semiconductor layer. For example, the source gas comprises a silicon source gas, germanium source gas or combination gas thereof. At this time, the source gas is decomposed by heat energy in the chamber, thereby generating silicon nuclei, germanium nuclei or silicon germanium (Si-Ge) nuclei. Thus, the silicon nuclei, the germanium nuclei or the silicon germanium nuclei are bonded with dangling bonds at the surface of the semiconductor substrate. As a result, a semiconductor layer is formed on the entire surface of the semiconductor substrate.
After formation of the semiconductor layer, the injection of the source gas is stopped and the etching gas, e.g., chlorine gas, is injected into the chamber. The etching gas reacts with the atoms of the semiconductor layer and a by-product gas compound is vented out of the chamber. Thus, the semiconductor layer formed on the insulating layer pattern is selectively removed. On the contrary, the semiconductor layer formed on the exposed semiconductor substrate still exists. This is because the adsorption coefficient at the surface of the insulating layer pattern is different from that of the exposed semiconductor substrate. Meanwhile, the surface of the semiconductor layer that exists on the exposed semiconductor substrate may be passivated with atoms of the etching gas during injection of the etching gas. That is to say, the atoms of the etching gas may be bonded with the atoms of the semiconductor layer.
After stopping the injection of the etching gas, the reducing gas such as hydrogen gas is injected into the chamber. The reducing gas reacts with the atoms of the passivation layer, thereby removing the passivation layer. As a result, a new semiconductor layer may be easily grown on the previous semiconductor layer during injection of the source gas in a subsequent step.
In addition, a dopant gas may be additionally injected into the chamber during at least one process of the processes of injecting the source gas, the etching gas and the reducing gas. Thus, it is easy to separately control the doping concentrations of the semiconductor layers. As a result, it is possible to obtain a desirable doping profile as per the depth of the total semiconductor layers. The dopant gas may be a phosphine (PH3) gas, a diborane (B2H6) gas or an arsine (AsH3) gas.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.